As is known in the art, with the Si CMOS VLSI integration capability passing the one-billion transistors level, the communication of electrical signals within various parts of a chip, between separate chips, and between printed circuit boards creates severe challenges with regard to speed and power consumption. Use of photonics instead of electronics has been sought as the best solution to this problem. Progress has been made in integrating passive optical components in Si technology, as reported in US patents in references such as, for example, U.S. Pat. Nos. 7,374,106; 7,286,726; 7,057,256; 6,930,82; 5,767,539, 6,154,475, 7,321,713, and 7,057,256.
As is also known in the art, vertical cavity surface emitting laser (VCSEL) and PIN photo-diodes with the well-established optical fibers have been proposed as indicated in this paragraph below as the best solution for short-range communication of very high-speed signals while maintaining low power consumption. The III-V VCSEL is recognized as the most suitable and ideal device for short-range optical communication as well as a variety of other applications, see for example: “VCSEL arrays for high speed optical links”, by Gulden, K. H.; Brunner, M.; Eitel, S.; Gauggel, H. P.; Hovel, R.; Hunziker, S.; Moser, M., Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2001. 23rd Annual Technical Digest, 21-24 Oct. 2001 Page(s): 53-56; “Smart integration and packaging of 2D VCSEL's for high-speed parallel links” by Kosaka, H.; IEEE Journal of Selected Topics in Quantum Electronics, Volume 5, Issue 2, March-April 1999 Page(s): 184-192, “780 nm VCSELs for home networks and printers” by Nakayama, H.; Nakamura, T.; Funada, M.; Ohashi, Y.; Kato, M.; Electronic Components and Technology Conference, 2004. Proceedings. 54th, Volume 2, 1-4 Jun. 2004 Page(s): 1371-1375 Vol.2
With the recent advances in the growth of III-V compounds on silicon substrate it is now possible to envision heterogeneous growth of VCSEL devices and photo-detectors onto Si substrate containing VLSI circuits. See for example, T. Ashley, L. Buckle, S. Datta, M. T. Emeny, D. G Hayes, K. P. Hilton, R. Jefferies, T. Martin, T. J. Philips, D. J. Wallis, P. J. Wilding and R. Chau, “Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications,” Electronics Letters, Vol. 43, No. 14, July 2007. S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, “Ultrahigh-Speed 0.5 V Supply Voltage I0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate,” IEEE Electron Device Letters, Vol. 28, No. 8, 2007, pp. 685-687. M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau, “Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 um) Composite Buffer Architecture for High-Speed and Low-Voltage (0.5V) Logic Applications,” International Electron Devices Meeting (IEDM) Technical Digest, 2007, pp. 625-628.
However, this vision is hampered by the fact that VCSEL epitaxial structures can be several microns (2 um-10 um) thick, and as such would be incompatible with the CMOS VLSI circuit planar topology and interconnects.